Department News
Microelectronics Packaging Technology. Current and Future
Seminar Date
2005-07-19
Author
임아주
Date
2005-07-14
Views
1950
1. 제 목 : Microelectronics Packaging Technology. Current and Future
2. 연 사 : Yeong K. Kim, Ph. D.
Research Faculty , Packaging Research Center , Georgia Institute of Technology
3. 일 시 : 2005년 7월 19일 화요일 16:00 ~ 17:00
4. 장 소 : 서울대학교 301동 1512호
5. 내 용 :
An electronic device of multi-functions, better performance, better portability and affordable price is always on demand. Multi-functions and better performance requires multiple chip packaging with high number of I/O ports. Better portability requires the compactness of the individual and assembled device. Cheap manufacturing process is prerequisite for price to be affordable. To achieve these multiplex goals, the design and assembly process have been continuously innovated for highly qualified product by introducing sophisticate part integration skill. ITRS 2003 roadmap identifies the needs for 45 nanometer of the technology node, and 100 micron pitch for flip chip array in 2010. Numerous issues emerge and exist as obstacles for this achievement. This is why microsystem packaging technology becomes more and more important. Packaging of microsystem is defined as the bridge that interconnects the IC’s and other components into a system level board to form electronic products. The Georgia Tech Packaging Research Center (PRC) has been a National Center in the U.S. for a decade, funded by the National Science Foundation, the State of Georgia, and the global electronics industry. The PRC has been pioneering the System-on-Package (SOP) paradigm. The SOP is all about thin film integration of embedded components leading to “system package or packaged–size system” with all system functions such as digital, RF, optical and sensors, and includes devices such as SOC, and packages or modules such as SIP. Miniaturization is achieved by component integration by thin film technologies. This seminar begins with general introduction of microelectronics packaging. A number of examples of the packaging structures and their features will be presented covering many types of fabrication/assembly from conventional to future technologies. Issues such as reliability and Cu/low-k will be also addressed. Technical issues to be solved for next generation packaging will be also discussed.
6. 연사약력
Research Faculty, Packaging Research Center, Georgia Inst. Tech., 2005~
Senior Manager, Samsung Techwin Co. Ltd., Seoul, Korea, 2003~2005
Research Associate, Northwestern University, Evanston, IL ., USA, 1999~2001
Team Leader, Korean Institute of Aerospace Technology, Korea, 1996~1998
Ph. D., Department of Aeronautical and Astronautical Engineering, University of Illinois at Urbana-Champaign, USA, 1996. 3.
BS, MS, Department of Aerospace Engineering, Inha University, Korea, 1986
7. 문 의 : 기계항공공학부 이 우 일 교수 (☎ 880-7116)
2. 연 사 : Yeong K. Kim, Ph. D.
Research Faculty , Packaging Research Center , Georgia Institute of Technology
3. 일 시 : 2005년 7월 19일 화요일 16:00 ~ 17:00
4. 장 소 : 서울대학교 301동 1512호
5. 내 용 :
An electronic device of multi-functions, better performance, better portability and affordable price is always on demand. Multi-functions and better performance requires multiple chip packaging with high number of I/O ports. Better portability requires the compactness of the individual and assembled device. Cheap manufacturing process is prerequisite for price to be affordable. To achieve these multiplex goals, the design and assembly process have been continuously innovated for highly qualified product by introducing sophisticate part integration skill. ITRS 2003 roadmap identifies the needs for 45 nanometer of the technology node, and 100 micron pitch for flip chip array in 2010. Numerous issues emerge and exist as obstacles for this achievement. This is why microsystem packaging technology becomes more and more important. Packaging of microsystem is defined as the bridge that interconnects the IC’s and other components into a system level board to form electronic products. The Georgia Tech Packaging Research Center (PRC) has been a National Center in the U.S. for a decade, funded by the National Science Foundation, the State of Georgia, and the global electronics industry. The PRC has been pioneering the System-on-Package (SOP) paradigm. The SOP is all about thin film integration of embedded components leading to “system package or packaged–size system” with all system functions such as digital, RF, optical and sensors, and includes devices such as SOC, and packages or modules such as SIP. Miniaturization is achieved by component integration by thin film technologies. This seminar begins with general introduction of microelectronics packaging. A number of examples of the packaging structures and their features will be presented covering many types of fabrication/assembly from conventional to future technologies. Issues such as reliability and Cu/low-k will be also addressed. Technical issues to be solved for next generation packaging will be also discussed.
6. 연사약력
Research Faculty, Packaging Research Center, Georgia Inst. Tech., 2005~
Senior Manager, Samsung Techwin Co. Ltd., Seoul, Korea, 2003~2005
Research Associate, Northwestern University, Evanston, IL ., USA, 1999~2001
Team Leader, Korean Institute of Aerospace Technology, Korea, 1996~1998
Ph. D., Department of Aeronautical and Astronautical Engineering, University of Illinois at Urbana-Champaign, USA, 1996. 3.
BS, MS, Department of Aerospace Engineering, Inha University, Korea, 1986
7. 문 의 : 기계항공공학부 이 우 일 교수 (☎ 880-7116)
